Hardware accelerators are increasingly used to extend the computational capabilities of baseline scalar processors to meet the growing performance and power requirements of embedded applications. The challenge to the designer is the extensive human effort required to identify the appropriate kernels to be mapped to gates, and to implement a network of accelerators to execute the kernels.
The levels of integration of modern field programmable gate arrays (FPGA's) have advanced to the point where complex Systems on a Chip (SoC's) with processors, accelerator IP, peripherals, and system software can be built and deployed very rapidly. Prior software tools have offered a plethora of predefined IP cores for frequently used kernels in multimedia, communications, networking, etc. However, existing software tools do not allow an application developer to extract computationally complex kernels from an application and map them to gates in an automated way.